Proposed scheme for Electronics, Trigger and Data Acquisition Systems for the INO prototype detector

INO eTRIDAS Team^*

Prepared by B.Satyanarayana, TIFR, Mumbai

1. Introduction

A 1m³ prototype detector is proposed to be built for studying feasibility of INO experiment. It will be made using 1m X 1m glass RPC detectors which are interleaved with 60mm thick iron plates. Considering an active detector thickness of about 20mm, this detector will consist of 12 layers in total. There will be two orthogonal signal pickup layers per active detector layer, placed above and below the detector. Considering a pickup strip pitch of 20mm, we need to instrument signals from about 1200 strips in total. Typical detector strip pulse characteristics are as shown in the following table.

Aim of the eTRIDAS is to implement the front-end electronics, trigger, data acquisition and monitoring systems for this detector, offering maximum flexibility in terms of design and operation, particularly in case of the trigger system. While considerable thought was given interms of its scalability for the full scale detector, the main emphasis of the design is however for quick implementation and thus or otherwise to use existing hardware and design expertise among the collaborative Institutions. Detailed discussions were held among the team members in consultation with other members of the collaboration on various suitable eTRIDAS schemes along with their merits and demerits.

2. Front-end electronics

Typical front-end chain of transimpedance preamplifier, threshold discriminator, pulse shaper and driver constitutes the first stage of the front-end electronics. The preamplifier should offer a good isolation to the discriminator from possible variable pickup strip characteristics. Discriminators will be used either with positive or with negative threshold for the pickup layers placed above and below a detector chamber. Pulse shaping is a requirement for the latch as well as the trigger system. Adequate fanout of the strip logic pulse is required for feeding the same to various subsystems of the eTRIDAS.

The second layer of front-end electronics essentially consists of various digital first level blocks of various eTRIDAS subsystems. These include logically ORed terms and memory lookup table based trigger front-ends, strip status latch circuits and appropriate multiplexing blocks of the detector logic signals for backend counting.

The interface between the front and back ends consists of a possible serial interfaces for downloading lookup tables into the trigger memory chips as well as for transmitting latch bit streams to the backends. Parallel address bus for monitoring multiplexing blocks is another interface requirement between the front and backends.

2. Back-end system

The backend system will be implemented on CAMAC standard. This layer will complete all the requirements of the eTRIDAS taking inputs from and providing interface services to the front-end. On the other hand, this layer will be interfaced to a PC based host via a CAMAC controller for providing the DAQ, data storage and user interface functions.

Functions such as final trigger generation (based on the lower level front-end trigger signals), trigger signal fanout, pre-trigger signal scalers, trigger identification latch etc are going to be implemented using a FPGA based trigger module similar to the one being developed at BARC. Scaler modules (used for monitoring) which are being used in the PACT experiment and TDC module (used for timing measurement) which is being used in Grapes experiment could be used in the back-end without any changes. The serial interfaces required for downloading lookup tables into front-end trigger circuits as well as for handling the latch signal readout could be met by RS-232 to CAMAC modules being desied for the Grapes experiment as well. Either Kinetic Systems made CAMAC controller and PC interfaces or those developed for the PACT experiment could be used for the CAMAC interface to the host PC. A simple parallel input/output module required for tasks such as selecting a strip channel for monitoring etc could be easily developed. Currently SINP was requested to develop this module.

2. Software issues

Linux drivers and other front-ends for the CAMAC hardware similar to the one described above has already been designed for the PACT experiment. These could largely be reused. PACT uses a CAMAC-PC interface of their own design. In case, for example a Kinetic Systems made hardware is planned to be used, we need to develop the front-ends afresh, but this is not considered to be very hard task as we have the required reference information on this hardware.

2. Other requirements

The glass RPC detectors are operated with a differential high voltage of about 5kV each on the two glass plates. We need to make an appropriate high voltage distribution consisting of ramp circuits etc so that high voltage to the individual detector layers could be controlled. SINP was again requested to take up this work.