Satyanarayana Bheesette
October 18, 2000
This register is used to reset the Muon Fanout Test Card and its internal sequencer as well as to control the HOTLink related operations such as BIST and SYS mode tests of MFC.
|
07 |
06 |
05 |
04 |
03 |
02 |
01 |
00 |
|
SW_ RESET |
NOT USED |
NOT USED |
START_ SYS |
RESET_ SEQ |
SVS |
BISTEN |
ENA/ TEN |
|
15 |
14 |
13 |
12 |
11 |
10 |
09 |
08 |
|
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
ENA/TEN Enables HOTLink transmitter when active. When inactive, puts HOTLink
in test mode during which the HOTLink sends K28.5 pad characters.
BISTEN Enables HOTLink's Built_In_Self_Test when active.
SVS Enables Send Violation Signal when active, during which HOTLink sends
continuous string of test characters.
RESET_SEQ Resets MFTC's internal sequencer when active. Usually done once
during startup.
START_SYS Starts MFC's SYS mode test when active.
SW_RESET Software reset of MFTC when active. Same effect as that of pushing the
front-panel RESET switch.
This register is used to write in the bits, which will generate corresponding interrupt signals in the Muon Fanout Card.
|
07 |
06 |
05 |
04 |
03 |
02 |
01 |
00 |
|
NOT USED |
VBD DONE |
NOT USED |
L2 ERR |
L1 ERR |
L2 BUSY |
L1 BUSY |
SRQ |
|
15 |
14 |
13 |
12 |
11 |
10 |
09 |
08 |
|
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
This register provides J2 backplane interface to the VME test crate.
|
07 |
06 |
05 |
04 |
03 |
02 |
01 |
00 |
|
SLV_ RDY |
RESET_ MRC |
L1REJ_ MRC |
L2REJ_ MRC |
L2AC_ MRC |
L1AC_ MRC |
INIT_ MRC |
STR_ MRC |
|
15 |
14 |
13 |
12 |
11 |
10 |
09 |
08 |
|
L1XN_ 07 |
L1XN_ 06 |
L1XN_ 05 |
L1XN_ 04 |
L1XN_ 03 |
L1XN_ 02 |
L1XN_ 01 |
L1XN_ 00 |
SLV_RDY is used during testing of MFC's VBD done interrupt. VBD done bit in the Interrupt Flag Register is first set. It generates VBD done interrupt fanning out through MFC. The service routine for this interrupt sets the MFC's SLV_RDY in its HOTLink Control register. The SLV_RDY bit in this backplane register is checked to make sure that the signal is transmitted back to the source of the interrupt. This procedure essentially simulates the VBD done procedure that VBD initiates in the real readout situation.
This register provides various status signals during the SYS mode test of MFC.
|
07 |
06 |
05 |
04 |
03 |
02 |
01 |
00 |
|
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
SYS_ RESULT |
SYS_ BUSY |
RP
|
|
15 |
14 |
13 |
12 |
11 |
10 |
09 |
08 |
|
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
NOT USED |
RP Read pulse is used during SYS mode testing of MFC.
SYS_BUSY If active, indicates that MFTC is busy during SYS mode test cycle.
SYS_RESULT If active, indicates that the result of the SYS mode test of MFC is a
success. This bit is reset on START_SYS in MFTC HOTLink Control
Register.